Gowin FPGA synthesis stuck on 95%

I am making a graphics card on the tang nano 20k board. I tried synthesising the design in the official IDE and it output:

[95%] Generate netlist file "/home/original2/Downloads/Gowin_V1.9.8.09_Education_linux/IDE/bin/VGA_out/impl/gwsynthesis/VGA_out.vg" completed

with no further updates for 40 minutes so far. I am on a 16 core system with 24GB of ram (the process is maxing out 1 core right now as well as using 6GB RAM). Why is it not progressing..

I do have a 60 by 80 array with 11 bit numbers in it if that is relevant