How can I improve this hacky SV assertion?
How can I improve this hacky SV assertion?
This is for an ADC. What I'm trying to do: when adc_sample goes low, grab hold of a value. Then when adc_data_en goes high, compare it with adc_data. Here's what I have so far:
property adc_deduces_voltage;
bit [7:0] true_voltage;
@(negedge adc_sample) (`true,true_voltage=input_channel)
##1 @(posedge adc_data_en)
// Values are sampled in the prepond region. This would be before
// adc_data_en is high, giving us old values. To make up for this, wait
// for one more clock cycle so that sampled values will be just after
// adc_data_en is high.
##1 @(posedge clock) (adc_data == true_voltage, $display("Pass. Actual: %d, ADC: %d", true_voltage, adc_data);
endproperty
assert property (adc_deduces_voltage);
Note the comment I inserted. The hacky bit of my code is waiting for the next rising edge of the clock so that I can avoid the issue of things being sampled in the prepone region.
Any thoughts on improving this? Is there a better way to do this?
Also, what if I wanted to do something like: wait for negedge adc_sample, then posedge adc_data_en then 20 clock cycles later carry out checks?