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InitialsDiceBearhttps://github.com/dicebear/dicebearhttps://creativecommons.org/publicdomain/zero/1.0/„Initials” (https://github.com/dicebear/dicebear) by „DiceBear”, licensed under „CC0 1.0” (https://creativecommons.org/publicdomain/zero/1.0/)IL
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4
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4
Joined
3 mo. ago

FPGA @lemmy.ml

How can I improve this hacky SV assertion?

Ask Electronics @discuss.tchncs.de

Unexpected large number of external interrupts except when logic analyzer is connected to pin.

Ask Electronics @discuss.tchncs.de

How come there are components in TO220 packages that supposedly take 100A given their small legs?

Ask Electronics @discuss.tchncs.de

How can I figure out which phases in a BLDC motor to power without knowing how its wound?

  • Thanks for your reply, that certainly a method I will try using.

    But in the case of my problem I think it won't work. Since adc_data is in the consequent of the implication, it will again be sampled in the prepone region and so take on the value before adc_data_en was asserted high, don't you think?

    In my code I set adc_data to its new value and at the same time set adc_data_en high. Perhaps I'm not supposed to do things this way? Is the usual practice to set something like adc_data to it's new value some time before the enable is asserted?