I have very little money and I just need something I can use to proxy traffic (HTTP mainly for my website) from the internet back to my server on my home network so that people can't tell where I live

Any dirt cheap hosting providers that just let me access some Unix system remotely?

Unlimited destruction on """the cloud""" of course !qin-shi-huangdi-fireball

So you got your technician's license? You get to do such fun activities as: call out on simplex FM voice for no one to respond or talk to the 70-year-old+ "repeater guys" who are on every day from 6 am - 6 pm about uhhhh radios, grilling, ex-wives if you want..... and then listen to the silence when everybody runs out of things to talk about in the presence of an "outsider" (someone who hasn't been on the repeater every day for 10+ years).

Not interested? That's fine, instead you can just listen to the activity on the repeater when they think no one else is around and hear interesting conversation topics like what the repeater guys would do if someone they were dating had an abortion including, but not limited to, "putting 2 between their eyes".

Not interested in even that? Okay, if your radio is capable of digital operation, you can connect to a system of linked repeaters and make contact with a different set of 70-year-old+ repeater guys. Once you make contact and talk a bit (maybe even have a good time listening to their stories if you're into that), you can look up their callsign and find their Twitter and find out they're REALLY RACIST and that probably the only reason they spoke to you in a polite manner or at all is cuz you have a "normal-sounding" male voice.

If this is what the self-policing culture of amateur radio is like (at least where I am in the United States currently) then we need to give many, many more Baofengs to unlicensed zoomers immediately

Anyway, that has been my experience so far in a rural area in the US. It hasn't been all bad (making contact with the International Space Station was cool) but yeah. I'm going back to a city soon, maybe it will be better there.

I really do want to get into this hobby and I love the technology (need to find the money sometime to do more packet stuff) but a lot of this type of stuff has been off-putting

I had no luck, couldn't hear anything and they (they includes their computers lol) couldn't hear me even though I had perfect line of sight to the station

I heard they have an APRS digipeater and other amateur radio equipment on board... maybe they turned it off recently or something

Info is sparse on the English-speaking internet

cross-posted from: https://hexbear.net/post/2781613

> Do any of you have experience with community mesh networking? It seems like a fun time and a good way to connect with people (socially and technically lol) in the community. Not to mention the possibility of providing at least limited internet access to people who can't access it by conventional means for whatever reason. A community mesh network might also have organizing possibilities - especially because the state or the cops or a company can't just shut it off or look inside it as easily

Do any of you have experience with community mesh networking? It seems like a fun time and a good way to connect with people (socially and technically lol) in the community. Not to mention the possibility of providing at least limited internet access to people who can't access it by conventional means for whatever reason. A community mesh network might also have organizing possibilities - especially because the state or the cops or a company can't just shut it off or look inside it as easily

https://www.siliconbunny.com/silicon-graphics-laptops/

My jaw dropped when I saw these, would be so cool to have one ;w;

The MIPS community is dying, upbear and comment if you're still a MIPS fan

What do they have to say?

A lot of hams think the Automatic Packet Reporting System is a system for broadcasting your location, and maybe your status. But the APRS is really a lot of local general-purpose low-speed message-switched* networks joined together by the big Internet (the one we're on rn) into another inter-network.

*Yeahh, it says packet in the name and is based on AX.25, but really the APRS is only capable of routing complete messages

It's primitive compared to the Internet but still very useful because of how widespread it is (I'm in some place you could describe as the "middle of nowhere" rn and there are still internet-connected APRS stations and digipeaters in range). The APRS is source-routed, meaning the sender of packets specifies the route they take through the network. You can specify a direct route for your packets to take through the network but most people leave this routing information set to the default on their radio, which is usually something like WIDE1-N,WIDE2-N where N specifies the number of times a packet is rebroadcast by any forwarding-capable station (digipeater) in range (this is how your position and status beacons get distributed to a wide area).

If you're familiar at all with the history of the APRS then you know its original purpose was to distribute information of local interest and it still does this but is now capable of so much more. You can send and receive text messages (including to the phones of non-hams), e-mails, get weather information, find out when satellites pass over your area, check into APRS nets, subscribe to groups and bulletins, and more.

Even if you're truly in the middle of nowhere with nothing and no one around, you can still keep in contact with people and beacon your location via one of the satellites carrying internet-connected APRS stations, no commercial satellite subscription and proprietary radio required (don't rely on it though lol). Even the International Space Station has an APRS station aboard

Kaepora Gaebora posting on main :did-you-get-all-that:

Artist is "Hail-NekoYasha", source at https://www.deviantart.com/hail-nekoyasha/art/O-RLY-NTNDO-33158110

Sometimes I like to look up the origin of the taglines. So I looked one up and found this old thread...

https://hexbear.net/post/1640059

I don't know this for sure, but I'm almost certain all of the other accts in this thread were eventually banned for being alts of DayOfDoom (HaruhiSuzumiya got herself banned during that thread about DayOfDoom's banning by being sus about it, the other got banned around the same time for unspecified ban evasion)

Literally arguing with themselves, completely artificial thread, and managed to get into a tagline

My honest reaction to this information:

!

The tagline from this thread is:

>Apart from further Luna Rossa flankers, would also recommend (re) testing more of the Prada Infusions for a less gourmand, sweet and/or woody, also fresher, crisper and more transparent take on somewhat similar notes, as well as the many AMen flankers, perhaps especially Pure Wood and Pure Tonka, while not entirely dismissing the other flankers and maybe also Kenzo Homme Boisee to certain extents

cross-posted from: https://hexbear.net/post/2429776

> Beanis bed reactor > > Great potential here

can someone else use my machine as a router to forward traffic to anywhere else on the internet?

I'm not entirely sure what the security implications of that would even be if true but probably nothing good

I don't have any other routes in my routing table other than my "default" route and this machine is reachable via a globally routable IPv4 address. Also I think there are probably other machines on the same subnet (cloud VPS)

He isn't even favored by StarClan, it's obvious he hasn't received his 9 lives smh

StarClan would never let a Clan leader commit a genocide under their watch !clueless

I wish nothing but pain and suffering upon people who project their reactionary opinions onto cute animals and internet personalities like big floppa

Link cuz I'm not a lib:

https://old.reddit.com/r/bigfloppa/comments/1b9j1sv/happy_womens_day/

!reddit-logo couldn't even manage a ratio:

!

cross-posted from: https://hexbear.net/post/2029720

> I was thinking of getting one of these as a cheap replacement for my broken (and disappointing) Pinephone Pro. > > What's the experience like?

I was thinking of getting one of these as a cheap replacement for my broken (and disappointing) Pinephone Pro.

What's the experience like?

My honest reaction: !oooaaaaaaauhhh

Link cuz I'm not a lib (beware: unmarked spoilers): https://tvtropes.org/pmwiki/pmwiki.php/WMG/WarriorCats

Don't look up the USSR on TVtropes, worst mistake of my life

!peter-running

>capitalizing "GUN" as though it mattered looked rather like hoplophobia

Link: https://news.ycombinator.com/item?id=24749158

cross-posted from: https://hexbear.net/post/1747735

> CPU-posting on main > > MTI = MIPS Technologies (company that made MIPS (Microprocessor without Interlocked Pipeline Stages) processors, they make RISC-V processors now lmao) > > At the time when the MIPS R10000, known as the "T5" while in development, was being designed, MTI had made a name for themselves as designers of high-performance computer microprocessors along the lines of the then-new philosophy of reduced instruction set computing (RISC). Actually, their R2000 design was the first commercially-available RISC microprocessor. By the time the T5 was being designed, they were no longer alone in the RISC microprocessor market. Several companies, including IBM and Motorola (joined together in the AIM alliance which produced PowerPC), DEC (who designed the Alpha line of RISC microprocessors after MTI owned them in the 80s when their radically simpler chips were performing better than VAXen), and Sun Microsystems (who were making the SPARC line of microprocessors) were now marketing RISC microprocessors. Not just even marketing but beating MTI in the market they had created. After trying and failing to develop their own complete computer systems alongside their chips, they were having financial difficulties until Silicon Graphics acquired MTI to secure availability of MIPS microprocessors for their famous ("it's a Unix system, I know this!") MIPS-based workstations and servers. Although their new (in 1993) R4000 and R4400 designs performed well compared to their contemporaries, they were quickly being made obsolete by MTI's competitor's new offerings and they were left with a problem: > > The MIPS R4000 and the R4400, which is essentially an R4000 with bigger on-die caches, were more or less just an architectural evolution from the R2000. The R4000 made its performance in much the same way as the R2000 did, the classic RISC design process mantra: "let's make it simpler" and thus be able to run it faster. In particular, what this means for the R4000, and what is a key difference from its predecessors and its contemporaries, is a technique called superpipelining. In an instruction pipeline, the maximum speed at which your processor can issue instructions is set by the pipeline stage which takes the longest to complete. Superpipelining is one way of addressing this problem: you can subdivide each pipeline stage into 2 simpler pipeline stages that individually complete faster and thus be able to clock your chip faster without problems. However, this has its limits. Eventually, it becomes impossible to further "deepen" the pipeline like this or clock the processor faster in general without other problems. This is why MTI's competitors opted for the analogous superscalar approach: you can duplicate functional units of your processor and have multiple instructions "in flight" at the same time and usually this also involves multiple pipelines. At the time MTI thought this approach would result in more consistently higher performance (not to mention save die space) but were quickly proven wrong when their competitor's superscalar (and often with other architectural tricks) chips were outperforming the R4000 in spite of MTI's fabrication partners constantly improving their process and releasing chips that ran at higher and higher speeds. > > Enter the MIPS R8000 (die not pictured here) in 1994, a weird and expensive 6-chip 4-way superscalar design meant for the high-end microprocessor market while the next-generation T5 (which would become the MIPS R10000, as mentioned earlier) was under development. It didn't sell well because of its high price and the fact that its integer performance, important for general-purpose computing applications, was lacking compared to the 200-MHz R4400 that was being sold by then. It did, however, have impressive floating-point performance, which landed many R8000-based systems in the TOP500 supercomputer list for a time. But this design could never be the high-performance and general-purpose processor MTI needed to compete with their competitor's offerings... > > Introduced in 1996, the MIPS R10000 (die IS pictured here) was a significant departure from the architecture of the R4000 (which more or less was directly derived from the first research done at Stanford University where MIPS was initially created over a decade earlier). Dropping the superpipeline approach, the R10000 is a 4-way superscalar processor even capable of executing instructions out of order! Another big change is that it has a branch predictor and speculatively executes instructions after a branch as opposed to the R4000, which used the classic MIPS "branch delay slot" technique to schedule one more instruction in the pipeline after a branch and then stall lol (they should have added even more delay slots, caring about binary compatibility is liberalism). It's hard to find benchmarks for something this old but this design performed at least several times faster than an R4400 at about the same clock speed! > > If you like my CPU posting and want me to post more in the future let me know > > Also ask me any questions if you want too and I'll try to answer

CPU-posting on main

MTI = MIPS Technologies (company that made MIPS (Microprocessor without Interlocked Pipeline Stages) processors, they make RISC-V processors now lmao)

At the time when the MIPS R10000, known as the "T5" while in development, was being designed, MTI had made a name for themselves as designers of high-performance computer microprocessors along the lines of the then-new philosophy of reduced instruction set computing (RISC). Actually, their R2000 design was the first commercially-available RISC microprocessor. By the time the T5 was being designed, they were no longer alone in the RISC microprocessor market. Several companies, including IBM and Motorola (joined together in the AIM alliance which produced PowerPC), DEC (who designed the Alpha line of RISC microprocessors after MTI owned them in the 80s when their radically simpler chips were performing better than VAXen), and Sun Microsystems (who were making the SPARC line of microprocessors) were now marketing RISC microprocessors. Not just even marketing but beating MTI in the market they had created. After trying and failing to develop their own complete computer systems alongside their chips, they were having financial difficulties until Silicon Graphics acquired MTI to secure availability of MIPS microprocessors for their famous ("it's a Unix system, I know this!") MIPS-based workstations and servers. Although their new (in 1993) R4000 and R4400 designs performed well compared to their contemporaries, they were quickly being made obsolete by MTI's competitor's new offerings and they were left with a problem:

The MIPS R4000 and the R4400, which is essentially an R4000 with bigger on-die caches, were more or less just an architectural evolution from the R2000. The R4000 made its performance in much the same way as the R2000 did, the classic RISC design process mantra: "let's make it simpler" and thus be able to run it faster. In particular, what this means for the R4000, and what is a key difference from its predecessors and its contemporaries, is a technique called superpipelining. In an instruction pipeline, the maximum speed at which your processor can issue instructions is set by the pipeline stage which takes the longest to complete. Superpipelining is one way of addressing this problem: you can subdivide each pipeline stage into 2 simpler pipeline stages that individually complete faster and thus be able to clock your chip faster without problems. However, this has its limits. Eventually, it becomes impossible to further "deepen" the pipeline like this or clock the processor faster in general without other problems. This is why MTI's competitors opted for the analogous superscalar approach: you can duplicate functional units of your processor and have multiple instructions "in flight" at the same time and usually this also involves multiple pipelines. At the time MTI thought this approach would result in more consistently higher performance (not to mention save die space) but were quickly proven wrong when their competitor's superscalar (and often with other architectural tricks) chips were outperforming the R4000 in spite of MTI's fabrication partners constantly improving their process and releasing chips that ran at higher and higher speeds.

Enter the MIPS R8000 (die not pictured here) in 1994, a weird and expensive 6-chip 4-way superscalar design meant for the high-end microprocessor market while the next-generation T5 (which would become the MIPS R10000, as mentioned earlier) was under development. It didn't sell well because of its high price and the fact that its integer performance, important for general-purpose computing applications, was lacking compared to the 200-MHz R4400 that was being sold by then. It did, however, have impressive floating-point performance, which landed many R8000-based systems in the TOP500 supercomputer list for a time. But this design could never be the high-performance and general-purpose processor MTI needed to compete with their competitor's offerings...

Introduced in 1996, the MIPS R10000 (die IS pictured here) was a significant departure from the architecture of the R4000 (which more or less was directly derived from the first research done at Stanford University where MIPS was initially created over a decade earlier). Dropping the superpipeline approach, the R10000 is a 4-way superscalar processor even capable of executing instructions out of order! Another big change is that it has a branch predictor and speculatively executes instructions after a branch as opposed to the R4000, which used the classic MIPS "branch delay slot" technique to schedule one more instruction in the pipeline after a branch and then stall lol (they should have added even more delay slots, caring about binary compatibility is liberalism). It's hard to find benchmarks for something this old but this design performed at least several times faster than an R4400 at about the same clock speed!

If you like my CPU posting and want me to post more in the future let me know

Also ask me any questions if you want too and I'll try to answer