I didn't know that I thought all RISC-V was open source :( I'm not as familiar with it as I'd like to be. I might just have to dive into it more and change that soon
He's being misquoted by the headline. He FEARS that it will make the same mistakes. Let's be clear about RISC is here in the first place: an open-source hardware architecture. Anyone with enough money and willpower to fork it for their needs will do so. It's anyone's game still. He's just simply saying that the same type of people who took over ARM and x86 are doomed to make the same mistakes. Not that RISC-V is bad.
I'm being pedantic here but RISC-V is not a hardware architecture as in something that you can send to a manufacturer and get it made. It is an ISA. How you implement those ISA is up to you. Yes there are open implementations but I think it is important to distinguish it.
smells like linus thinks there is going to be an ever increasing tech debt, and honestly, i think i agree with him on that one.
RISCV is likely going to eventually overstep it's role in someplaces, and bits and pieces of it will become archaic over time.
The gap between hardware and software level abstraction is huge, and that's really hard to fill properly. You just need a strict design criteria to get around that one.
I'm personally excited to see where RISCV goes, but maybe what we truly need is a universal software level architecture that can be used on various different CPU architectures providing maximum flexibility.
but maybe what we truly need is a universal software level architecture that can be used on various different CPU architectures providing maximum flexibility.
Then again, if you don't have the JVM/JRE, Java won't work, so first you need to write it in another language and in such a way that it works across a bunch of different ARM and x86 processors.
software level architecture that can be used on various different CPU architectures providing maximum flexibility.
I've only done a little bare metal programming, but I really don't see how this is possible. Everything I've used is so vastly different, I think it would be impossible to create something like that, and have it work well.
theoretically you could do it by defining an architecture operations standard, and then adhering to that somewhat when designing a CPU. While providing hardware flexibility as you could simply, not implement certain features, or implement certain other features. Might be an interesting idea.
That or something that would require minimal "instruction translation" between different architectures.
It's like x86. except if most of the features were optional.
He doesn't list what the mistakes will be. He said that he fears that because hardware people aren't software people, that they will make the same mistakes that x86 made, which were then made by Arm later.
He did mention that fixing those mistakes was faster for Arm than x86, so that brings hope that fixing the mistakes on Risc V will take less time
Instruction creep maybe? Pretty sure I've also seen stuff that seems to show that Torvalds is anti-speculative-execution due to its vulnurabilities, so he could also be referring to that.
Counterintuitive but more instructions are usually better. It enables you (but let's be honest the compiler) to be much more specific which usually have positive performance implications for minimal if any binary size. Take for example SIMD which is hyper specific math operations on large chunks of data. These instructions are extremely specific but when properly utilized have huge performance improvements.
Just a reminder the RISC-V architecture is not open source as many think it is only the instruction set is open source. We remain far from a truly open/libre hardware for now
Sorry, but that is completely wrong. RISC-V is an ISA, nothing less, nothing more, and it is completely, 100% open-source. The licensing of the hardware implementations is a different matter, but that's outside of the scope of RISC-V. As I said, it is just an ISA.
It's open source nature protects against that. People mistake Linus as being in the same boat as Stallman but Linus was only open source by circumstance, he kind infamously doesn't seem to appreciate the role open source played in his own success.
It already directly addresses the mistakes of x86 and ARM. I don't know what he is so worried about.
I'll say to you what I said to the other commentor: RISC-V is an ISA, nothing less, nothing more, and it is 100% open-source. It is not trying to be anything else. Yes, hardware implementations from processor vendors can have different licensing and be proprietary, but that is not the fault of RISC-V, nor does that have anything else to do with it. RISC-V, as an ISA, and only an ISA, is completely open-source and not liable for the bs of OEMs.
What I read here is just a vague critic from him of the relation between hard- and software developer. Which will not change just because the ISA is open source. It will take some iterations until this is figured out, this is inevevable.
Soft- and hardware developers are experts in their individual fields, there are not many with enough know-how of both fields to be effective.
Linus also points out, that because of ARM before, RISC-V might have a easier time, on the software side, but mistakes will still happen.
IMO, this article doesn't go into enough depths of the RISC-V specific issues, that it warrants RISC-V in the title, it would apply to any up and coming new ISA.